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bug: Timer0 clock source set to external (T0CKI) instead of internal #30

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opened 2026-08-02 05:25:20 +00:00 by time · 1 comment
time commented 2026-08-02 05:25:20 +00:00
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OPTION_REG was set to 0b11111111, which sets TMR0CS=1 (external clock from RA4/T0CKI). RA4 is analog input, so no clock edge arrives and Timer0 never increments. ISR never fires, tx_done never asserts, transmit_packet hangs forever. Fix: set OPTION_REG = 0b11011111 to use internal Fosc/4 clock.

OPTION_REG was set to 0b11111111, which sets TMR0CS=1 (external clock from RA4/T0CKI). RA4 is analog input, so no clock edge arrives and Timer0 never increments. ISR never fires, tx_done never asserts, transmit_packet hangs forever. Fix: set OPTION_REG = 0b11011111 to use internal Fosc/4 clock.
time commented 2026-08-03 04:00:15 +00:00
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Fixed in PR #39: OPTION_REG corrected to 0b11011111 (TMR0CS=0, internal Fosc/4 clock).

Fixed in PR #39: OPTION_REG corrected to 0b11011111 (TMR0CS=0, internal Fosc/4 clock).
time closed this issue 2026-08-03 04:06:57 +00:00
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