feat: Boot-time configuration mode (GPIO test → UART session) #46

New issue

Open

opened 2026-08-29 20:53:27 +00:00 by time · 0 comments

time commented

2026-08-29 20:53:27 +00:00

Contributor

UART is available on this rev. The EUSART is software-pinnable via the APFCON register:

TX: RA0 (TXCKSEL=0) or RA4 (TXCKSEL=1)
RX: RA1 (RXDTSEL=0) or RA5 (RXDTSEL=1)

So a 2-wire UART fits on this rev. Current rev GPIO: RA0=bias circuit (out), RA1=AN1 (analog, unused), RA2=TX DATA (RF), RA3=digital in (free), RA4=AN3 (analog, sensor), RA5=TX CTRL (RF). The board is being rewired to free up pins and match a future rev; the final UART TX/RX + config-test pin assignment will follow that.

TX-sleep invariant (firmware): the RF TX enters Sleep when DATA is held low longer than tOFFT (20 ms on this board) with CTRL stable. So whenever the firmware is not talking to the TX it must hold DATA=0 and CTRL=0. During a UART config session the TX pins are idle-low, so the TX stays asleep. The firmware must track TX asleep/awake as state. (A hardware MUX to physically isolate the TX pins is planned for the next rev — electrical side.)

Open questions:

which GPIO to use for the config-mode test, and high-vs-low polarity
how the session ends (explicit "done" command, timeout, or power-cycle)
whether to debounce the pin / require it to be held for N ms
final pin assignment (UART TX/RX, config-test pin) once the rewire is settled

On initial power-on, the MCU samples a GPIO to decide whether to enter a configuration session instead of the normal transmit loop. If the pin reads a configured level, the device activates its EUSART and runs a UART session to load the config block into EEPROM (#45). Otherwise it boots normally. This is the mechanism that lets a user configure a device without reflashing. **UART is available on this rev.** The EUSART is software-pinnable via the APFCON register: - TX: RA0 (`TXCKSEL=0`) or RA4 (`TXCKSEL=1`) - RX: RA1 (`RXDTSEL=0`) or RA5 (`RXDTSEL=1`) So a 2-wire UART fits on this rev. Current rev GPIO: RA0=bias circuit (out), RA1=AN1 (analog, unused), RA2=TX DATA (RF), RA3=digital in (free), RA4=AN3 (analog, sensor), RA5=TX CTRL (RF). The board is being rewired to free up pins and match a future rev; the final UART TX/RX + config-test pin assignment will follow that. **TX-sleep invariant (firmware):** the RF TX enters Sleep when DATA is held low longer than tOFFT (20 ms on this board) with CTRL stable. So whenever the firmware is not talking to the TX it must hold **DATA=0 and CTRL=0**. During a UART config session the TX pins are idle-low, so the TX stays asleep. The firmware must track TX asleep/awake as state. (A hardware MUX to physically isolate the TX pins is planned for the next rev — electrical side.) Open questions: - which GPIO to use for the config-mode test, and high-vs-low polarity - how the session ends (explicit "done" command, timeout, or power-cycle) - whether to debounce the pin / require it to be held for N ms - final pin assignment (UART TX/RX, config-test pin) once the rewire is settled

time referenced this issue

2026-08-29 21:47:00 +00:00

feat: EEPROM-backed device configuration store #45