TMR0 timing off 4x (Fosc/4 not Fosc) and tx_emulator baud rate hardcoded #24

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opened 2026-07-31 22:42:43 +00:00 by time · 0 comments

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2026-07-31 22:42:43 +00:00

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The firmware Timer0 formula 256 - (_XTAL_FREQ / (TX_BAUD * 2)) assumed Fosc as the Timer0 clock source, but PIC12LF1840 Timer0 uses Fosc/4 (Section 20.1, Figure 20-1 of the datasheet). At 500kHz Fosc this means 125kHz Timer0 clock, 8μs ticks instead of 2μs, resulting in 500 bps actual data rate instead of the intended 2000 bps. The rtl_433 decoder and tx_emulator were both configured for 2000 bps, so none of the three components were actually aligned. Fix: divide by 4 in the TMR0_RELOAD formula (131→225, half-bit 1000μs→248μs). Also add --tx-baud CLI argument to tx_emulator to derive its half-bit rate from the firmware's TX_BAUD instead of hardcoding 4000.

The firmware Timer0 formula `256 - (_XTAL_FREQ / (TX_BAUD * 2))` assumed Fosc as the Timer0 clock source, but PIC12LF1840 Timer0 uses Fosc/4 (Section 20.1, Figure 20-1 of the datasheet). At 500kHz Fosc this means 125kHz Timer0 clock, 8μs ticks instead of 2μs, resulting in 500 bps actual data rate instead of the intended 2000 bps. The rtl_433 decoder and tx_emulator were both configured for 2000 bps, so none of the three components were actually aligned. Fix: divide by 4 in the TMR0_RELOAD formula (131→225, half-bit 1000μs→248μs). Also add `--tx-baud` CLI argument to tx_emulator to derive its half-bit rate from the firmware's TX_BAUD instead of hardcoding 4000.

time referenced this issue from a pull request that will close it,

2026-07-31 22:43:18 +00:00

Fix TMR0 timing (Fosc/4) and sync tx_emulator baud rate #23

time referenced this issue from a pull request that will close it,

2026-08-01 16:05:39 +00:00

Fix TMR0 timing (Fosc/4) and sync tx_emulator baud rate #27