Fix TMR0 timing (Fosc/4) and sync tx_emulator baud rate #23

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time commented

2026-07-31 22:42:29 +00:00

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Fixes #24

Root cause: PIC12LF1840 Timer0 clock = Fosc/4, not Fosc (datasheet Section 20.1 / Figure 20-1). The Timer0 reload formula did not account for this, causing a 4x timing error.

Impact: Firmware transmitted at 500 bps while rtl_433 and tx_emulator expected 2000 bps — none of the three components were actually aligned.

Changes:

Firmware: TMR0_RELOAD = 256 - (Fosc/4 / (TX_BAUD * 2)) → 225 instead of 131, half-bit 248μs instead of 1000μs
tx_emulator: Added --tx-baud CLI arg (default 2000) so half-bit rate is derived from firmware TX_BAUD, not hardcoded

Fixes #24 **Root cause:** PIC12LF1840 Timer0 clock = Fosc/4, not Fosc (datasheet Section 20.1 / Figure 20-1). The Timer0 reload formula did not account for this, causing a 4x timing error. **Impact:** Firmware transmitted at 500 bps while rtl_433 and tx_emulator expected 2000 bps — none of the three components were actually aligned. **Changes:** - **Firmware:** TMR0_RELOAD = 256 - (Fosc/4 / (TX_BAUD * 2)) → 225 instead of 131, half-bit 248μs instead of 1000μs - **tx_emulator:** Added --tx-baud CLI arg (default 2000) so half-bit rate is derived from firmware TX_BAUD, not hardcoded

time added 1 commit

2026-07-31 22:42:30 +00:00

Fix TMR0 timing (Fosc/4) and sync tx_emulator baud rate 4d1ad5e09b

The firmware Timer0 formula assumed Fosc as the clock source, but PIC12LF1840
uses Fosc/4 (125kHz at 500kHz Fosc). This caused the actual data rate to be
500 bps instead of the intended 2000 bps.

Also add --tx-baud CLI argument to tx_emulator so its half-bit rate is derived
from the firmware's TX_BAUD rather than hardcoded.

Firmware:
  TMR0_RELOAD: 131 -> 225 (half-bit 1000us -> 248us)
  Data rate: 500 bps -> ~2000 bps

tx_emulator:
  Added --tx-baud parameter (default 2000, matches firmware TX_BAUD)
  half_bit_rate now derived from tx_baud * 2 instead of hardcoded 4000